1. Technical Field
The embodiment relates to a semiconductor integrated circuit, and in particular, to a data writing apparatus and method for a semiconductor integrated circuit.
2. Related Art
FIG. 1 is a circuit diagram illustrating a data writing apparatus for a semiconductor integrated circuit according to the related art.
A data writing apparatus for a semiconductor integrated circuit according to the related art is configured to include inverters IV1 and IV2, a buffer 1, first to eleventh flip-flops FF1 to FF11, first to fourth multiplexers 2 to 5, a data clock generator 6, a decoder 7, global data lines GIO0 to GIO3, and a write driver block 8, as shown in FIG. 1.
The first to seventh flip-flops FF1 to FF7 are configured to align data DATA_IN in response to signals DSRP and DSFP, which are in synchronization with a rising edge and a falling edge of a data strobe signal DQS, respectively, so as to generate aligned data ALGNF1, ALGNR1, ALGNF0, and ALGNR0.
The data clock generator 6 is configured to shift a write command WT_CMD by (WL+2)tCK so as to generate a data clock DCLK. Here, “WL” represents write latency and “tCK” represents one cycle time of a clock CLK.
The decoder 7 is configured to decode addresses A0 and A1 so as to generate a decoded signal SOSEB<0:3>. The decoded signal SOSEB<0:3> is commonly input to all of the first to fourth multiplexers 2 to 5.
The first to fourth multiplexers 2 to 5 are configured to each select one of the aligned data ALGNF1, ALGNR1, ALGNF0, and ALGNR0 according to the decoded signal SOSEB<0:3> such that the aligned data selected by the first to fourth multiplexers 2 to 5 are mutually different, and to output the selected data at the same timing. For example, according to the decoded signal SOSEB<0:3>, the first to fourth multiplexers 2 to 5 may sequentially select the aligned data ALGNF1, ALGNR1, ALGNF0, and ALGNR0 or may select the aligned data ALGNR1, ALGNF0, ALGNR0, and ALGNF1.
The eighth to eleventh flip-flops FF8 to FF11 are configured to receive outputs of the first to fourth multiplexers 2 to 5 and then outputs them to the global data lines GIO0 to GIO3 with the same timing in response to the data clock DCLK.
The write driver block 8 is configured to receive data GIO_Q0 to GIO_Q3 transmitted through the global data lines GIO0 to GIO3 and write the data in a memory area.
FIG. 2 is a timing chart illustrating the operation of the data writing apparatus for a semiconductor integrated circuit according to the related art.
The first to seventh flip-flops FF1 to FF7 align data DATA_IN in response to the signals DSRP and DSFP so as to generate the aligned data ALGNF1, ALGNR1, ALGNF0, and ALGNR0.
The aligned data ALGNF1, ALGNR1, ALGNF0, and ALGNR0 are selected by the first to fourth multiplexers 2 to 5 according to the decoded signal SOSEB<0:3> and are output.
The eighth to eleventh flip-flops FF8 to FF11 output the outputs of the first to fourth multiplexers 2 to 5 to the global data lines GIO0 to GIO3 in response to the data clock DCLK.
As described above, the data writing apparatus for a semiconductor integrated circuit according to the related art aligns the data DATA_IN by using the first to seventh flip-flops FF1 to FF7 and then transmits the aligned data to the global data lines GIO0 to GIO3 at the same time in response to the data clock DCLK.
In other words, logic levels of data of all of the global data lines GIO0 to GIO3 are transitioned at the same time.
The related art of FIG. 1 having been described above is configured to include four global data lines GIO0 to GIO3. Actually, in the case of a DDR2, 64 global data lines exist, and in the case of a DDR3, 128 global data lines exist.
As the sizes of semiconductor integrated circuits are reduced, the area ratio occupied by the global data lines to the whole area of semiconductor integrated circuit gradually increase, such that the widths of global data lines are reduced, which results in reducing the intervals between neighboring global data lines.
Therefore if logic levels of data of neighboring global data lines of the global data lines which transmit data at the same time transition to opposite logic levels, they may have negatively influence each other, resulting in distortion and delay in data transmission.
This may also cause errors in data write timings so as not to sufficiently write data in memory cells. As a result, degradation in the refresh capability or an increase in write discovery time tWR may be caused and a serious error such as no data write may also be caused.